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Corresponding Author

Enab, Yehia

Subject Area

Electronics and Communication Engineering

Article Type

Original Study

Abstract

The need for high speed digital storage/retrieval and digital communication systems with error detection and error correction capabilities raises a significant problem to the implementation of error control encoding and decoding. Traditional inplementation has been accomplished through the use of feedback shift register networks. These networks, although being convenient to implement represent a slow process in the overall system since they involve the shifting of code words to generate the error control bits/syndrome. Parallel implementation provides a fast solution, however, it poses a significant complexity to the encoder/decoder implementation. This paper introduces a new implementation for a fast encoder/decoder using analog neural networks. With neural nets as the basic building blocks, the error contra bits/syndrome are asynchronously generated using Op Amps and resistor elements. The problem of fan-in and fan-out inherent in digital implementation is also avoided.

Keywords

Neural network; Switching circuits; Computer interfacing; Error detection and Error correction; Encoders and Decoders

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