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Subject Area

Electronics and Communication Engineering

Article Type

Original Study

Abstract

This paper introduces a 10-Gb/s single-loop, half-rate delay-locked loop (DLL)-based clock and data recovery (CDR) circuit for forwarded-clock (FC) wireline transceivers. The proposed CDR employs a differential ring oscillator (RO) with sub-feedback loops structure for multi-phase clock generation with a single-loop operation. An Alexander phase detector utilizing a flip-flop based on an improved true single-phase clock (TSPC) logic with split outputs is adopted. The proposed DLL-based CDR is an optimized solution in terms of area and power for FC wireline transceivers. The recovered clock exhibits an RMS jitter of 590 fs and a peak-to-peak jitter of 3.8 ps. The circuit achieves a power consumption of 7.3 mW from a 1.2 V supply, resulting in a commendable power efficiency of 0.73 pJ/bit. The implementation of the proposed DLL-based CDR employs 65-nm CMOS technology, while occupying an active area of 0.0056 mm2

Keywords

Clock and data recovery (CDR), voltage-controlled delay line (VCDL), phase detectors, wireline transceivers.

Creative Commons License

Creative Commons Attribution 4.0 License
This work is licensed under a Creative Commons Attribution 4.0 License.

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