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Subject Area

Electronics and Communication Engineering

Article Type

Original Study

Abstract

This paper introduces a DAC-based four-level pulse-amplitude modulation (PAM-4) driver capable of operating at data rates up to 80 Gb/s in 65-nm CMOS technology. A replica-based termination calibration loop is proposed to preserve driver linearity across process, voltage, and temperature (PVT) variations. The proposed driver achieves a relative level mismatch (RLM) of 99.3%. In addition, the transmitter demonstrates a vertical eye opening of 134.8 mV and a horizontal eye opening of 0.44 UI under worst-case conditions.

Keywords

VM; SST; NRZ; PAM-4; RLM

Creative Commons License

Creative Commons Attribution 4.0 License
This work is licensed under a Creative Commons Attribution 4.0 License.

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